In conventional design and verification techniques, large hierarchical designs have two stages of timing closure, these are block-level timing closure and full-chip timing closure. In block level timing closure, for each individual block, a user must determine constraints for each block and achieve timing closure after the place and route operation is complete. The constraints for individual blocks are often decided in an ad-hoc manner, by assuming some numbers for input and output delays and giving some margin for top-level net delays. Once all blocks are hardened (i.e. place and route is completed), the blocks are integrated at the top-level. This conventional methodology is shown in FIG. 1, where blocks B1, B2, up to . . . . BN are individual place and route (PNR) blocks. The characteristics of this approach include that it is a bottom up approach, the input arrival times and output required times are numbers assumed at the block level, and the full-chip activities are started after blocks are frozen.
The conventional methodology results in iterations because each block is synthesized without looking into how the block fits into the full chip environment. The block level timing constraints for input setup and output data valid were assumed numbers, derived without taking into account the actual net delays at the top level.
Disadvantages of the conventional approach include that in the conventional approach top-level net delays are not measured accurately since this can be estimated only after top level routing is completed, and the design and verification process is quite iterative and time consuming, and not well suited to automation.
FIG. 2 shows a timing diagram with delay budget for block level design. In FIG. 2 the B1 and B2 timing budgets can not incorporate top level net delays accurately because this is unknown during the initial synthesis and place and route operations. The actual top level net delays may be significantly off from initial estimates causing iterations during full-chip Static Timing Analysis.
It would be desirable to have a design and verification technique for block level design that accurately determines net delays and reduces the number of iterations required.